The present invention relates to a C language-based hard/soft cooperative verifying simulator for speeding up logic verification at hardware design and system level design and cooperative verification of hardware and software.
A simulator using an HDL (Hardware Description Language) has heretofore been used for cooperative verification for verifying a real-time OS (Operation System), device drivers and software task operations comprising applications/programs and the like on a simulation model in which operations of CPUs (Central Processing Units), memories, buses, peripheral devices, etc. of a built-in system. Since, however, the simulator using the HDL is difficult to provide speed-up, there has been proposed and used a simulator of a system level using a C language-based model description language such as described in, for example a patent document 1 [(Japanese Unexamined Patent Publication No. 2005-293219) and refer to a patent document 2 (Japanese Unexamined Patent Publication No. 2006-23852) and a non-patent document 1 (Open SystemC Initiative, “SystemC 2.0.1 Language Reference Manual”, Revision1.0)]. With speeding-up of simulation, pre-verification of a system level including software is enabled before detailed design of hardware and the design of LSI (Large Scale Integration circuit) are completed.
The normal C language encounters difficulties in realizing simulations on which delay times of hardware and the number of execution cycles of a CPU are reflected. Therefore, a hardware model description language such as SpecC, SystemC or the similar language has been proposed and put forward for standardization.
In a SystemC simulator, processes operated in parallel in smaller module units, called Threads each capable of being started from one task placed during start-up have been realized. wait functions for controlling the simulation times have been prepared for the SystemC simulator. The wait function advances the simulation time managed by the simulation kernel (body) of the SystemC simulator by an elapsed time given as an argument for a wait function invocation and performs context switching control between the threads being executed in parallel. Incidentally, the context designates the state of a processor that is executing a simulation. Context switching means that the context of each thread under execution is switched to that of another thread.
Thus, when a cooperative verifying simulation is done using the SystemC simulator, the threads that perform parallel operations are sequentially switched and controlled by the wait functions, thereby making it possible to perform the verification of a system level including software.
In the cooperative verifying simulation using the SystemC simulator, however, the context switching control between the threads is performed each time the wait functions are invoked. Therefore, the overhead increases due to the frequently-executed context switching control, thus resulting in a reduction in simulation speed.